Ultra-Low Voltage Nano-Scale thoughts presents an in-depth dialogue of the cutting-edge nanometer and sub-1-V reminiscence LSIs which are enjoying decisive roles in energy unsleeping structures. rising difficulties among the gadget, circuit, and approach degrees are systematically lined by way of trustworthy high-speed operations of reminiscence cells and peripheral common sense circuits. The effectiveness of options at machine and circuit degrees can be defined at size via clarifying noise elements in an array, or even crucial variations in ultra-low voltage operations among DRAMs and SRAMs. in addition, several types of on-chip voltage converters essential to resolve issues of inner power-supply managements are greatly mentioned. This authoritative monograph addresses those layout demanding situations for reminiscence and circuit engineers in addition to for researchers and scholars who're attracted to ultra-low voltage nano-scale reminiscence LSIs.
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761–769, July 1994.  S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, “1-V energy offer high-speed electronic circuit know-how with multithreshold-voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, pp. 847–854, Aug. 1995.  okay. Itoh, “Reviews and clients of low-power reminiscence circuits” (invited), LowPower CMOS layout, A. Chandrakasan and R. Brodersen, Eds. , Wiley–IEEE Press, NJ, pp. 313–317, 1998.  M. Hasegawa, M. Nakamura, S. Narui, S. Ohkuma, Y. Kawase, H. Endoh, S. Miyatake, T. Akiba, okay. Kawakita, M. Yoshida, S. Yamada, T. Sekiguchi, I. Asano, Y. Tadaki, R. Nagai, S. Miyaoka, okay. Kajigaya, M. Horiguchi and Y. Nakagome, “A 256Mb SDRAM with subthreshold leakage present suppression,” ISSCC Dig. Tech. Papers, pp. 80–81, Feb. 1998.  S. Narendra, S. Borkar, V. De, D. Antoniadis and A. Chandrakasan, “Scaling of stack impact and its program for leakage reduction,” Proc. ISLPED, pp. 195–199, Aug. 2001.  C. Akrout, J. Bialas, M. Canada, D. Cawthron, J. Corr, B. Davari, R. Floyd, S. Geissler, R. Goldblatt, R. Houle, P. Kartschoke, D. Kramer, P. McCormick, N. Rohrer, G. Salem, R. Schulz, L. Su and L. Whitney, “A 480-MHz RISC microprocessor in a zero. 12-um Leff CMOS expertise with copper interconnects,” IEEE J. Solid-State Circuits, vol. 33, pp. 1609–1616, Nov. 1998.  H. Morimura and N. Shibata, “A 1-V 1-Mb SRAM for moveable equipment,” Proc. ISLPED, pp. 61–66, Aug. 1996.  ok. Itoh, R. Hori, H. Masuda, Y. Kawajiri, H. Kawamoto and H. Katto, “A unmarried 5V 64K dynamic RAM,” ISSCC Dig. Tech. Papers, pp. 228–229, Feb. 1980.  I. Fukushi, R. Sasagawa, M. Hamaminato, T. Izawa and S. Kawashima, “A lowpower SRAM utilizing greater cost move experience amplifiers and a dual-Vth CMOS circuit scheme,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 142–145, June 1998.  A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, ok. Mistry, T. Ghani, S. Borkar and V. De, “Effectiveness of opposite physique bias for leakage keep an eye on in scaled twin Vt CMOS ICs,” Proc. ISLPED, pp. 207–212, Aug. 2001.  H. Mizuno, ok. Ishibashi, T. Shimura, T. Hottori, S. Narita, okay. Shiozawa, S. Ikeda and ok. Uchiyama, “A 18- A standby present 1. 8-V 200-MHz microprocessor with self-substrate-biased data-retention mode,” IEEE J. Solid-State Circuits, vol. 34, pp. 1492–1500, Nov. 1999.  T. Sakata, M. Horiguchi, M. Aoki and ok. Itoh, “Two-dimensional powerline choice scheme for low subthreshold-current multi-gigabit DRAMs,” Proc. ESSCIRC, pp. 131–134, Sep. 1993.  okay. Seta, H. Hara, T. Kuroda, M. Kakumu and T. Sakurai, “50% active-power saving with out velocity degradation utilizing standby strength aid (SPR) circuit,” ISSCC Dig. Tech. Papers, pp. 318–319, Feb. 1995.  okay. Kumagai, H. Iwaki, H. Yoshida, H. Suzuki, T. Yamada and S. Kurosawa, “A novel powering-down scheme for low Vt CMOS circuits,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 44–45, June 1998. References 181  M. Mizuno, ok. Furuta, S. Narita, H. Abiko, I. Sakai and M. Yamashina, “ElasticVt CMOS circuits for a number of on-chip strength control,” ISSCC Dig. Tech. Papers, pp. 300–301, Feb. 1996.  G. Kitsukawa, M. Horiguchi, Y. Kawajiri, T. Kawahara, T. Akiba, Y.