Minimizing and Exploiting Leakage in VLSI Design

By Nikhil Jayakumar

Power intake of VLSI (Very huge Scale built-in) circuits has been starting to be at an alarmingly quick expense. This raise in strength intake, coupled with the expanding call for for portable/hand-held electronics, has made strength intake a dominant situation within the layout of VLSI circuits at the present time. ordinarily, dynamic (switching) strength has ruled the full energy intake of an IC. even though, as a result of present scaling traits, leakage energy has now develop into an important component to the full strength intake in VLSI circuits. Leakage strength relief is principally vital in portable/hand-held electronics akin to cell-phones and PDAs. This e-book provides innovations aimed toward decreasing leakage energy in electronic VLSI ICs. the 1st strategy reduces leakage in the course of the selective use of excessive threshold voltage sleep transistors. the second one method reduces leakage by way of utilising the optimum opposite physique Bias (RBB) voltage. This e-book additionally exhibits readers the right way to flip the leakage challenge into a chance, by utilizing sub-threshold logic.

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113 10. 1 10. 2 Schematic of PLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 117 hold up variety with and with out our dynamic physique bias strategy . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 119 section detector and cost pump circuit . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . a hundred and twenty part detector waveforms whilst PLA hold up lags BCLK . . . . . . .. . . . . . . . . . . 121 part detector waveforms whilst PLA hold up leads BCLK . . . . . .. . . . . . . . . . . 121 Dynamic adjustment of PLA hold up and VNbulk with VDD version . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 124 instance of a conventional charge-pump DLL (adapted from [1]) . . . . . . . . . . one hundred twenty five 10. three 10. four 10. five 10. 6 10. 7 ninety four ninety five ninety six ninety seven eleven. 1 eleven. 2 Schematic of PLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 132 energy dissipated, hold up within the 4 modes with various VDD (Vbulkn D zero V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 134 eleven. three energy and hold up in all 4 modes with various Vbulkn .. . . . . .. . . . . . . . . . . 134 eleven. four power intake and hold up within the dynamic modes, with various Vbulkn.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . one hundred thirty five eleven. five power intake, hold up within the dynamic modes with various VDD (Vbulkn D zero V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 136 eleven. 6 power intake over diverse task components (Vbulkn D zero V) . . . . . 136 eleven. 7 Circuit outfitted as a chain of 4 PLAs . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 138 eleven. eight overall power intake in keeping with cycle for various common sense depths at 25ı C (Vbulkn D zero V) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 139 eleven. nine overall strength intake in line with cycle for various good judgment depths at 50ı C (Vbulkn D zero V) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . a hundred and forty eleven. 10 overall strength intake consistent with cycle for various good judgment depths at seventy fiveı C (Vbulkn D zero V) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . one hundred forty eleven. eleven overall strength intake consistent with cycle for various good judgment depths at a hundredı C (Vbulkn D zero V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 141 12. 1 12. 2 12. three 12. four 12. five 12. 6 NPLA-based asynchronous micropipelined circuit .. . . . . . . . . . . .. . . . . . . . . . . a hundred forty five Micropipelined PLA handshaking logic.. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 146 Verilog simulation of our method .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 146 Decomposition of a circuit right into a community of PLAs . . . . . . . . . . . .. . . . . . . . . . . 148 Schematic of the PLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 149 structure view of the PLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . one hundred fifty List of Figures xxvii 14. 1 14. 2 14. three 14. four 14. five 14. 6 BFSK transmitter structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 164 method architecture.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . a hundred sixty five Schematic view of PLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 166 Timing diagram of NPLAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 167 electronic to analog converter .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . 171 universal resource amplifier ..

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