Low-Power Variation-Tolerant Design in Nanometer Silicon

Layout issues for low-power operations and robustness with appreciate to adaptations mostly impose contradictory requisites. Low-power layout options corresponding to voltage scaling, dual-threshold project and gate sizing may have huge detrimental effect on parametric yield lower than approach diversifications. This ebook specializes in circuit/architectural layout suggestions for reaching low energy operation less than parameter adaptations. We ponder either common sense and reminiscence layout features and canopy modeling and research, in addition to layout method to accomplish concurrently low strength and version tolerance, whereas minimizing layout overhead. This e-book will speak about present business practices and rising demanding situations at destiny expertise nodes.

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Adaptive strategies could be utilized to regulate telephone voltages counting on the inter-die approach nook to lessen the dominant failure, and for that reason, the final failure fee. The bankruptcy has mentioned a self repairing SRAM that makes use of adaptive physique bias for post-silicon adaptive fix of SRAM array, leading to greater reminiscence yield. edition tolerance for SRAM peripherals and yield enhancement tools for experience amplifiers were mentioned. eventually, the bankruptcy has mentioned an adaptive voltage scaling solution to provide a trade-off among version tolerance and occasional energy in multimedia functions, the place a few point of error might be tolerated through the applying. five Low-Power and Variation-Tolerant reminiscence layout 181 References 1. Agarwal A, Hai Li, Roy okay (Feb 2003) A single-Vt low-leakage gated-ground cache for deep submicron. IEEE J Solid-State Circuits 38(2):319–328 2. Bhavnagarwala A, Tang X, Meindl JD (Apr 2001) The effect of intrinsic equipment fluctuations on CMOS SRAM phone balance. IEEE J Solid-State Circuits 36:658–665 three. Bhavnagarwala A, Kosonocky SV, Kowalczyk SP, Joshi RV, Chan YH, Srinivasan U, Wadhwa JK (Jun 2004) A transregional CMOS SRAM with unmarried, good judgment VDD and dynamic energy rails. In: Symposium on VLSI Circuits, Honolulu, hello, pp 292–293 four. Borkar S, Karnik T, Narendra S, Tschanz J, Keshavarzi A, De V (2003) Parameter edition and impression on circuits and microarchitecture. layout Automation convention, Anaheim, CA, pp 338–342 five. Burnett D, Erington ok, Subramanian C, Baker okay (Jun 1994) Implications of primary threshold voltage adaptations for high-density SRAM and common sense circuits. In: Symposium on VLSI know-how, Honolulu, hello, pp 15–16 6. Chandrakasan A, Bowhill WJ, Fox F (2001) layout of high-performance microprocessor circuits. IEEE, Piscataway, NJ 7. Chappell B, younger I (Apr 2003) VDD modulated SRAM for hugely scaled, excessive functionality cache. US Patent 6556471 eight. Cheemalavagu S, Korkmaz P, Palem KV (Sept 2004) extremely low-energy computing through probabilistic algorithms and units: CMOS gadget primitives and the energy-probability dating. In; overseas convention on stable nation units and fabrics, Tokyo, pp 402–403 nine. Chen G, Kandemir M (2005) Optimizing tackle code iteration for array-intensive DSP purposes. In: overseas symposium on code iteration and optimization, San Jose, CA, pp 141–152 10. Chen Q, Mahmoodi H, Bhunia S, Roy ok (Nov 2005) effective trying out of SRAM with optimized march sequences and a singular DFT strategy for rising mess ups because of approach adaptations. IEEE Trans VLSI Syst 13(11):1286–1295 eleven. Cho M, Schlessman J, Wolf W, Mukhopadhyay S (2009) Accuracy-aware SRAM: a reconfigurable low strength SRAM structure for cellular multimedia functions. In: Asia and South Pacific layout automation convention, Yokohama, pp 823–828 12. Cochran WG (1977) Sampling options, third edn. Wiley, manhattan, long island thirteen. Djahromi AK, Eltawil AM, Kurdahi FJ, Kanj R (Mar 2007) pass layer mistakes exploitation for competitive voltage scaling. IEEE overseas symposium on caliber digital layout, San Jose, CA, pp 192–197 14.

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